1. Field of the Invention
This invention relates to the fabrication of a structure adapted for the construction of an integrated circuit network and more particularly to the fabrication of a structure having dielectrically isolated active semiconductor regions in which dielectrically isolated semiconductor devices are formed.
2. Prior Art
There have been a number of prior art approaches to the problem of isolating electrical elements which form an integrated circuit. The term integrated circuit is employed herein and includes thin film integrated circuits as well as semiconductor monolithic and hybrid integrated circuits. One prior art approach for dielectrically isolating active elements is disclosed in U.S. Pat. No. 3,158,788 issued to J. T. Last on Nov. 24, 1964. Last employed a barrier of added dielectric isolating material to isolate the elements of the circuit. While this method has definite advantages, it does not provide maximum elemental density. Other prior art patents such as U.S. Pat. No. 3,100,276 issued to O. L. Meyer on Aug. 6, 1963 and U.S. Pat. No. 3,189,798 issued to C. E. Benjamin on June 15, 1965 have attempted various arrangements of grooves alone or in combination with pn junctions to partially isolate the semiconductor devices forming integrated circuits.
U.S. Pat. No. 3,695,160 issued to Sloan, Jr. et al., on Apr. 25, 1972, teaches an orientation dependent etching technique employed in the fabrication of monolithic semiconductor devices forming an integrated circuit network providing both electrical isolation of the devices and an increase in elemental density. The electrical isolation is attained by an epitaxial layer of one conductivity type placed on a substrate of an opposite conductivity type. This patent does not teach dielectric isolation of semiconductor devices. The Armstrong devices are located in a monocrystalline wafer upon which an oxide layer is grown or deposited, and the wafer is mounted on a polycrystalline substrate. The devices are chemically etched to the polycrystalline substrate through the oxide layer to dielectrically isolate each device. This is presently a standard technique for dielectrically isolating semiconductor devices. Difficulties have arisen in applying this technique to fabrication of microwave semiconductor devices because the monocrystalline substrate must be of a controlled thickness to provide electrically matched devices. U.S. Pat. No. 3,489,961 issued to Frescara et al. on Jan. 13, 1970 teaches dielectric isolation of microwave semiconductor devices. Frescara's patent discloses a method of forming an integrated circuit structure including the steps of:
1. depositing a first type n+ epitaxial layer onto an n-type monocrystalline wafer;
2. depositing a second n-type epitaxial layer on the first epitaxial layer;
3. doping the second n-type epitaxial layer with donor and acceptor impurities to form p and n-type regions of a semiconductor device;
4. forming an oxide mask over the second epitaxial layer exposing regions for metallization;
5. metallizing these regions to form ohmic contacts with p and n regions of the semiconductor device;
6. adhering an oxide coated supporting substrate to the second layer of the wafer; and
7. etching grooves through to the oxide layer of the supporting substrate to isolate each semiconductor device.
U.S. Pat. No. 3,579,391 entitled "Method of Producing Dielectric Isolation for Monolithic Circuit" issued to James L. Buie on May 18, 1971, teaches a method of forming a structure of dielectrically isolated semiconductor regions which include the steps of lapping and polishing an active n-type region within which semiconductor devices are to be formed. This presently practiced method of the prior art begins with an nn+ epitaxial wafer wherein the epitaxial wafer has a first layer of monocrystalline n-type silicon of a predetermined thickness and a second layer of monocrystalline n-type silicon epitaxially deposited onto the first layer which is substantially thinner than the first layer. A plurality of grooves are etched through the second layer and approximately halfway through the first layer. Silicon dioxide is thermally grown both on the surface of the grooves and on the second surface of the wafer. Polycrystalline silicon is deposited onto the silicon dioxide layer. The first layer of a n-type silicon is lapped until a portion of the silicon dioxide layer in each groove is exposed thereby forming a plurality of active semiconductor device regions. The lapping and polishing processes often damage the first layer of n-type silicon. Furthermore, the lapping and polishing processes do not always insure identical thicknesses of isolated active semiconductor regions within the limit imposed by the original wafer. Often dielectrical isolation of an active semiconductor region is not achieved because of variations in thickness and parellelism of the original wafer.
The principal disadvantage of the above disclosed prior art method is in the difficulty in lapping parallel to the original surface and in controlling the thickness of the original undiffused portion of the dielectrically isolated first epitaxial layer to within plus or minus one-half micron. In all the above methods of the prior art the basic problem is to control the thickness of the devices so that they may be used for microwave application. It should be noted that the other patents have drawings which are not drawn to scale and that layers of semiconductor material which are five to seven microns in thickness are difficult to achieve and are in fact not realized by any of the above prior art methods. The present invention combines the use of an epitaxial technique and a sputter etching technique to produce dielectrically isolated active semiconductor regions which are uniform both in thickness and in parallelism. It is therefore an object of the present invention to provide uniform structures of dielectrically isolated active semiconductor regions on a common wafer. It is another object of the present invention to provide an increase in the density of dielectrically isolated active semiconductor regions over that normally achieved by prior art methods of dielectrically isolating active semiconductor regions. It is also another object of the present invention to eliminate damaging material removal procedures used in the prior art methods of dielectrically isolating active semiconductor regions.
It is still another object of the present invention to provide a method for dielectrically isolating active semiconductor regions on a wafer which is insensitive to nonuniformities in the thickness and parallelism of the original wafer.